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dual 3 a, 20 v synchro nous step - down regulator with integra ted high - side mosfet data sheet adp2323 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by imp lication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features input voltage : 4.5 v to 20 v 1 % output accuracy integrated 90 m? typical high - side mosfet flexible o utput c onfiguration dual o utput: 3 a/3 a parallel s ingle o utput: 6 a programmable s witching f requency: 250 khz to 1.2 mhz external s ynchronization input with programmable phase shift, or internal clock output selectable pwm or pfm mode operation adjustable current limit for small inductor external c ompensation and s oft s tart start up into precharged output support ed by adisimpower ? design tool applications communication s i nfrastructure networking and s erver s industrial and instrumentation healthcare and medical intermediate power rail conversion dc - to - dc point of load applications typical application circuit intvcc r t op1 c c1 r c1 c ss1 c int c dr v c in1 c bst1 c bst2 l1 m1 m2 l2 v in v in v out1 c out1 c out2 v out2 r bot1 r t op2 r c2 c c2 c ss2 c in2 r bot2 r osc fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 09357-001 figure 1. general description the adp2323 is a full featured , dual output , step - down dc - to - dc regulator based on current - mode architecture . the adp2323 integra te s two high - side p ower m osfet s and two low - side driver s for the exter nal n - c hannel m osfet s . t he two pulse - width mod - ulation ( pwm ) cha nnel s can be configured to deliver dual 3 a output s or a parallel - to - single 6 a output. t he regulator operates from input voltage s of 4.5 v to 20 v , and the output voltage can be as low as 0.6 v . the switching frequency can be programmed between 2 5 0 khz and 1.2 m hz , or synchronized to an external clock to minimize interference in multi rail app lications. t he dual pwm channe ls run 180 out of phase , thereby reducing input current ripple as well as reducing the size of the input capacitor. the bidirectional synchronization pin can be programmed at a 60 , 90, or 120 phase shift, providing the po ssibility for a stackable mu lti phase power solution . t he adp2323 can be set to operate in pulse - frequency modulation ( pfm ) mo de at a light load for higher efficiency or in forced pwm for noise sensitive applic ation s . external compensation and s oft start provide design flexibility . independent enable inputs and power good outputs provide reliable power sequen cing. to enhance system reliability, the device also includes undervoltage lockout (uvlo) , over voltage pr otection ( ovp ) , over current pro - tection ( ocp ) , and thermal shutdown (tsd) . t he adp2323 operates over the ? 40 c to +125 c junction temperature range and is available in a 32- lead lfcsp _wq package . 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficienc y (%) output current (a) v out = 5v v out = 3.3v 09357-002 figure 2. efficiency vs. output current at v in = 1 2 v, f sw = 600 khz
adp2323 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration a nd function descriptions ............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 15 control scheme .......................................................................... 15 pwm mode ................................................................................. 15 pfm mode ................................................................................... 15 precision enable/shutdown ...................................................... 15 separate input voltages ............................................................. 15 internal regulator (intvcc) .................................................. 15 bootstrap circuitry .................................................................... 16 low - side driver .......................................................................... 16 oscillator ..................................................................................... 16 synchronization .......................................................................... 16 soft start ...................................................................................... 16 peak current - limit and short - circuit protection ................. 16 voltage tracking ......................................................................... 17 parallel operation ....................................................................... 17 power good ................................................................................. 17 overvoltage protection .............................................................. 17 undervoltage lockout ............................................................... 18 thermal shutdown .................................................................... 18 applications information .............................................................. 19 adisimpower design tool ....................................................... 19 input capacitor selection .......................................................... 19 output voltage setting .............................................................. 19 voltage conversion limitations ............................................... 19 current - limit setting ................................................................ 19 inductor selection ...................................................................... 20 output capacitor selection ....................................................... 20 low - side power device selection ............................................ 21 programming uvlo input ...................................................... 21 compensation components design ....................................... 21 design example .............................................................................. 23 output voltage setting .............................................................. 23 current - limit setting ................................................................ 23 frequency setting ....................................................................... 23 inductor selection ...................................................................... 23 output capacitor selection ....................................................... 23 low - side mosfet selection ................................................... 24 compensation components ..................................................... 24 soft start time programming .................................................. 24 input capacitor selection .......................................................... 24 external components recommendation .................................... 25 typical application circuits ......................................................... 26 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision histor y 6/12 rev. 0 to rev. a change to features section ............................................................. 1 added adisimpower design tool section ................................. 19 7 / 1 1 rev ision 0: initial version
data sheet adp2323 rev. a | page 3 of 32 functional block diagram + ? + 0.6v i ss1 ss1 fb1 comp1 amp1 control logic and mosfet driver with anticross protection bst1 sw1 i1 max i1 max hiccup mode nfet1 vdrv dl1 0.7v 0.54v ovp pgood1 pvin1 uvlo en1 current- limit selection oscillator pgnd scfg sync rt clk1 clk2 slope ramp1 slope ramp2 5v regulator en1_buf adp2323 en1_buf en2_buf intvcc pvin1 gnd mode mode_buf skip mode threshold mode_buf skip cmp1 slope ramp1 clk1 ? + zero current cmp vdrv + trk1 + ? + ? 1.2v 4a 1a ocp cmp1 + ? + ? + ? + ? driver driver boost regulator + ? + 0.6v i ss2 ss2 fb2 comp2 amp2 control logic and mosfet driver with anticross protection bst2 sw2 i2 max i2 max hiccup mode nfet2 vdrv dl2 0.7v 0.54v ovp pgood2 pvin2 uvlo en2 current- limit selection en2_buf skip mode threshold mode_buf skip cmp2 slope ramp2 clk2 ? + zero current cmp + trk2 + ? + ? 1.2v 4a 1a ocp cmp2 + ? + ? + ? + ? driver driver boost regulator 09357-042 a cs1 a cs2 figure 3. functional block diagram
adp2323 data sheet rev. a | page 4 of 32 specifications pvin 1 = pvin2 = 12 v at t j = ? 40 c to + 125 c, unless otherwise noted. table 1 . parameters symbol test conditions /comments min typ max units power input (pvinx pins) power input voltage range v pvin 4.5 20 v quiescent current (pvin1 + pvin2) i q mode = gnd, no switching 3 5 ma shutdown current (pvin1 + pvin2) i shdn en 1 = en2 = gnd 50 100 a p vin x undervoltage lockout threshold uvlo p vin x r ising 4. 3 4. 5 v p vin x f alling 3.5 3.8 v feedback (fbx pins) fb x regulation voltage 1 v fb p vi n x = 4.5 v to 20 v 0. 5 9 4 0. 6 0. 6 0 6 v fb x bias current i fb 0.01 0.1 a error amplifier ( compx pin s) transconductance g m 230 300 370 s ea source current i source 2 5 45 6 5 a ea sink current i sink 2 5 45 65 a internal regulator (intvcc pin ) intvcc voltage 4.75 5 5.25 v dropout voltage i intvcc = 3 0 ma 4 0 0 mv regulator current limit 40 75 120 ma sw itch node (sw x pin s) high - side on resistanc e 2 v bst to v sw = 5 v 90 1 3 0 m ? sw x peak current limit r ilim = f loating , v bst to v sw = 5 v 4 4.8 5.8 a r ilim = 47 k ? , v bst to v sw = 5 v 2.3 3 3.7 a r ilim = 15 k ? , v bst to v sw = 5 v 0.8 1. 5 2.2 a sw x minimum on time 3 t min_on 13 0 ns sw x minimum off tim e 3 t min_off 150 ns low - side driver ( dl x pins ) rising t im e 3 c dl = 2 .2 n f, s ee figure 19 20 ns falling t im e 3 c dl = 2 .2 nf , s ee figure 22 10 ns sourcing resistor 4 6 ? sinking resistor 2 4.5 ? oscillator (rt pin) pwm switching fre quency f sw r osc = 100 k ? 530 600 670 khz pwm frequ e ncy range 250 120 0 khz sync hronization (sync p in ) sync input sync configured as input synchronization range 3 0 0 120 0 k hz minimum on pulse width 100 n s minimum off pulse width 100 n s high threshold 1.3 v low threshold 0.4 v sync output sync configured as output frequency on sync pin f clkout f sw khz positive pulse time 100 ns s oft start (ss x pin s) ssx pin source current i ss 2.5 3.5 4.5 a
data sheet adp2323 rev. a | page 5 of 32 parameters symbol test conditions /comments min typ max units t racking input (trkx pins) trk x input voltage range 0 600 mv trk x -to -fb x offset voltage trk x = 0 mv to 500 mv ? 10 +10 mv trk x input bias current 100 na power good (pgood x pin s) power good rising threshold 87 90 93 % power good hysteresis 5 % power good deglitch time from fb x to pgood x 16 clock cycle pgood x leakage current v pgood = 5 v 0 .1 1 a pgood x output low voltage i pgood = 1 ma 50 1 00 mv en able (enx pins) en x rising threshold 1.2 1.28 v en x falling threshold 1.02 1.1 v en x source current en voltage below falling threshold 5 a en voltage above rising thresh old 1 a mode (mode pin) input high voltage 1.3 v input low voltage 0.4 v thermal thermal shutdown threshold 150 c thermal shutdown hysteresis 15 c 1 tested in a feedback loop that adjusts v fb to achieve a specified voltage on the compx pi n. 2 p in - to - pin measurements . 3 guaranteed by design .
adp2323 data sheet rev. a | page 6 of 32 absolute maximum rat ings table 2 . paramet er rating p vin 1 , pvin 2, en1, en2 ? 0.3 v to + 2 2 v sw1, sw2 ? 1 v to + 22 v bst1, bst2 v sw + 6 v fb 1 , fb2, s s1, ss2,comp1, comp2 , pgood1, pgood2, trk1, trk2 , scfg, sync, rt, mode ? 0.3 v to +6 v intvcc, vdrv, dl1, dl2 ? 0.3 v to +6 v pgnd to gnd ? 0.3 v to +0.3 v temperature range operating ( junction ) ? 40 c to +125 c storage ? 65 c to +150 c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabi lity. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. boundary condition ja is measured using natural convection on a jedec 4 - layer board, and the exposed pad is soldered to the printed c ircuit board (pcb) with thermal vias . table 3 . thermal resistance package type ja unit 32- lead lfcsp_wq 32.7 c/w esd caution
data sheet adp2323 rev. a | page 7 of 32 pin configuration and fu nction descriptions 1s w 1 2 bst1 3 dl1 4 pgnd 5 vdrv 6 dl2 7 bst2 8 sw2 24 23 22 21 20 19 18 17 pgood1 notes 1. the exposed pad should be soldered to an external gnd plane. scfg sync gnd intvcc rt mode pgood2 9 10 11 12 13 14 15 16 fb2 comp2 ss2 trk2 en2 pvin2 pvin2 sw2 32 31 30 29 28 27 26 25 fb1 comp1 ss1 trk1 en1 pvin1 pvin1 sw1 top view (not to scale) adp2323 09357-003 figure 4. pin configuration (top view) table 4. pin function descriptions pin no. mnemonic description 1 pgood1 power-good output (open drain) for channel 1. a pull-up resistor of 10 k to 100 k is recommended. 2 scfg synchronization configuration input. the scfg pin conf igures the sync pin as an input or output. connect scfg to intvcc to configure sync as an output. using a resistor to pull down to gnd configures sync as an input with various phase shift degrees. 3 sync synchronization. this pin can be configured as an in put or an output. when conf igured as an output, it provides a clock at the switching frequency. when config ured as an input, this pi n accepts an external clock to which the regulators are synchronized and the phase sh ift is configured by scfg. note that when sync is configured as an input, the pfm mode is disabled and the device works on ly in continuous conduction mode (ccm). 4 gnd analog ground. connect to the ground plane. 5 intvcc internal 5 v regulator output. the ic control circuits are powered from this voltage. place a 1 f ceramic capacitor between intvcc and gnd. 6 rt connect a resistor between rt and gnd to program the switching frequency between 250 khz and 1.2 mhz. 7 mode mode selection. when this pin is connected to intv cc, the pfm mode is disabled and the regulator works only in ccm. when this pin is connected to ground, th e pfm mode is enabled. if the low-side device is a diode, the mode pin must be connected to ground. 8 pgood2 power-good output (open drain) for channel 2. a pull-up resistor of 10 k to 100 k is recommended. 9 fb2 feedback voltage sense input for channel 2. connect to a resistor divider from the channel 2 output voltage, v out2 . connect fb2 to intvcc for parallel applications. 10 comp2 error amplifier output for channel 2. connect an rc network from comp2 to gnd. connect comp1 and comp2 together for parallel applications. 11 ss2 soft start control for channel 2. connect a capacitor from ss2 to gnd to program the soft start time. for parallel applications, ss2 remains open. 12 trk2 tracking input for channel 2. to track a master voltage, drive this pin from a voltage divider from the master voltage. if the tracking function is not used, connect trk2 to intvcc. 13 en2 enable pin for channel 2. an external resistor divide r can be used to set the turn-on threshold. when not using the enable pin, connect en2 to pvin2. 14, 15 pvin2 power input for channel 2. connect pvin2 to the input power source, and connect a bypass capacitor between pvin2 and ground. 16, 17 sw2 switch node for channel 2. 18 bst2 supply rail for the gate drive of channel 2. place a 0.1 f capacitor between sw2 and bst2. 19 dl2 low-side gate driver output for channel 2. connect a resistor between dl2 and pgnd to program the current-limit threshold of channel 2. 20 vdrv low-side driver supply input. connect vdrv to intvcc. place a 1 f ceramic capacitor between the vdrv pin and pgnd. 21 pgnd driver power ground. connect to the source of the synchronous n-channel mosfet. 22 dl1 low-side gate driver output for channel 1. connect a resistor between this pin and pgnd to program the current-limit threshold of channel 1.
adp2323 data sheet rev. a | page 8 of 32 pin no. mnemonic description 23 bst1 supply r ail for the gate driv e of channel 1 . p lace a 0.1 f capacitor between sw 1 and bst 1 . 24, 25 sw1 switch n ode for channel 1. 26, 27 pvin1 power input for channel 1 . this pin is the power input for channel 1 and provide s power for the internal regulator. connect to the input power source and connect a bypass capacitor between pvin1 and ground. 28 en1 enable p in for channel 1. an e xternal resistor divi der can be used to set the turn - on threshold. when not us ing the e nable pin, connect the en 1 pin to pvin 1 . 29 trk1 tracking i nput for channel 1. to track a master voltage, drive this pin from a voltage divider from the master voltage. if the tracking func tion is not used, connect trk1 to intvcc . 30 ss1 soft start control for channel 1 . t o program the soft start time , c onnect a capacitor from ss 1 to gnd. 31 comp1 error amplifier o utput for channel 1 . connect an rc network from comp 1 to gnd. connect comp1 and comp2 together for a parallel application . 32 fb1 feedback voltage sense inpu t for c hannel 1. connect to a resistor divider from the channel 1 output voltage , v out 1 . exposed pad solder t he exposed pad to an external gnd plane.
data sheet adp2323 rev. a | page 9 of 32 typical perform ance characteristics o perating conditions : t a = 25 c, v in = 12 v , v out = 3.3 v, l = 4.7 h, c out = 2 47 f, f sw = 600 khz , u nless otherwise noted . 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficienc y (%) output current (a) v out = 5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v induc t or: cdrh105rnp-3r3n mosfe t : fds8880 09357-005 figure 5 . efficiency at v in = 12 v, f sw = 600 khz, fpwm 0 10 20 30 40 50 60 70 80 90 100 efficienc y (%) v out = 3.3 v , fpwm v out = 3.3 v , pfm v out = 5 v , fpwm v out = 5 v , pfm 09357-006 induc t or: cdrh105rnp-3r3n mosfe t : fds8880 0.01 0.1 1 10 output current (a) figure 6. efficiency at v in = 12 v, f sw = 60 0 khz, pfm 10 15 20 25 30 35 40 4 6 8 10 12 14 16 18 20 shutdown current (a) v in (v) 09357-007 t j = ?40c t j = +25c t j = +125c figure 7. shutdown current vs. v in 0 0.5 1.0 1.5 2.0 2.5 3.0 output current (a) induc t or: cdrh105rnp-6r8n mosfe t : fds8880 v out = 5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 09357-008 50 55 60 65 70 75 80 85 90 95 100 efficienc y (%) figure 8. efficiency at v in = 12 v, f sw = 300 khz, fpwm 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficienc y (%) output current (a) v out = 3.3 v , fpwm v out = 3.3 v , pfm v out = 5 v , fpwm v out = 5 v , pfm 09357-009 induc t or: cdrh105rnp-6r8n mosfe t : fds8880 figure 9. effi ciency at v in = 12 v, f sw = 300 khz, pfm 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 4 6 8 10 12 14 16 18 20 quiescent current (ma) v in (v) t j = ?40c t j = +25c t j = +125c 09357-010 figure 10 . quiescent current vs. v in
adp2323 data sheet rev. a | page 10 of 32 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 100 120 uvlo threshold (v) temper a ture (c) rising f alling 09357-0 1 1 figure 11 . uvlo threshold vs. temperature 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 ?40 ?20 0 20 40 60 80 100 120 en source current (a) temper a ture (c) 09357-012 figure 12 . en source current at v en = 1.5 v 594 596 598 600 602 604 606 feedback vo lt age (mv) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-013 figure 13 . fb voltage vs. temperature 1.00 1.05 1.10 1.15 1.20 1.25 1.30 enable threshold (v) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) rising f alling 09357-014 figure 14 . en threshold vs. temperature 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 ?40 ?20 0 20 40 60 80 100 120 en source current (a) temper a ture (c) 09357-015 figure 15 . en source current at v en = 1 v 250 260 270 280 290 300 310 320 330 340 350 transconduc t ance (s) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-016 figure 16 . g m vs. t emperature
data sheet adp2323 rev. a | page 11 of 32 540 560 580 600 620 640 660 frequenc y (khz) r osc = 100k? ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-017 figure 17 . frequency v s. temperature 50 60 70 80 90 100 1 10 120 130 mosfet resis t or (m?) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-018 figure 18 . m osfet r dson v s. temperature 09357-019 ch1 5.00v ch2 2.00v m20.0ns a ch1 1.10v 2 1 t 31.20% sw dl figure 19 . low - s ide driver rising edge waveform , c dl = 2 .2 nf 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 4 6 8 10 12 14 16 18 20 volt age (v) v in (v) 09357-020 figure 20 . intvcc voltage vs. v in 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 ssx pin source current (a) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-021 figure 21 . ssx pin source current v s. temperature 09357-022 ch1 5.00v ch2 2.00v m20.0ns a ch1 1.10v 2 1 t 60.20% sw dl figure 22 . low - s ide driver falling edge waveform , c dl = 2 .2 nf
adp2323 data sheet rev. a | page 12 of 32 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-023 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 peak current limit (a) figure 23 . current - limit threshold vs. temperature, r ilim = floating 0.8 1.0 1.2 1.4 1.6 1.8 2.0 peak current limit (a) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-024 figure 24 . current - limit th reshold vs. temperature, r ilim = 15 k? 09357-025 ch1 10.0mv b w ch2 10.0v ch4 500ma ? m2.00s a ch2 9.40v 2 4 1 t 50.20% sw i l v out (ac) figure 25 . discontinuous conduction mode (dcm) 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 peak current limit (a) ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) 09357-026 figure 26 . current - limit threshold vs. temperature, r ilim = 47 k? 09357-027 ch1 10.0mv b w ch2 10.0v ch4 2.00a ? m2.00s a ch2 5.80v 2 4 1 t 50.00% sw v out (ac) i l figure 27 . continuous conduction mode (ccm) 09357-028 ch1 100mv b w ch2 10.0v ch4 1.00a ? m400s a ch1 ?12.0mv 2 4 1 t 60.40% v out (ac) i l sw figu re 28 . power saving mode
data sheet adp2323 rev. a | page 13 of 32 09357-029 ch1 2.00v b w ch3 10.0v ch2 5.00v ch4 2.00a ? m1.00ms a ch2 1.80v 1 2 4 3 t 50.40% v out en pgood i out figure 29 . soft start with full load 09357-030 ch1 100mv b w ch4 1.00a ? m200s a ch4 1.00a 1 4 t 70.20% v out (ac) i out figure 30 . load transient response , 0.5 a to 2.5 a 09357-031 ch1 2.00v b w ch2 10.0v ch4 2.00a ? m10.0ms a ch1 960mv 1 2 4 t 20.60% v out sw i l figure 31 . output short 09357-032 ch1 2.00v b w ch3 10.0v ch2 5.00v ch4 1.00a ? m1.00ms a ch2 1.80v 1 2 4 3 t 50.40% v out en pgood i l f igure 32 . pre charge d o utput 09357-033 ch1 20.0mv b w ch3 5.00v b w ch2 5.00v m1.00ms a ch1 ?8.00mv 1 2 3 t 72.00% sw v out (ac) v in i out figure 33 . line transient response , v in from 8 v to 14 v, i out = 3 a 09357-034 ch1 2.00v b w ch2 10.0v ch4 2.00a ? m10.0ms a ch1 1.28v 1 2 4 t 60.40% v out sw i l figure 34 . output short recovery
adp2323 data sheet rev. a | page 14 of 32 09357-035 ch1 10.0v ch3 5.00v ch2 10.0v m1.00s a ch3 2.90v 1 2 3 t 50.20% sync sw2 sw1 figure 35 . ext ernal synchronization with 60 phase shift 09357-036 ch1 10.0v ch3 5.00v ch2 10.0v m1.00s a ch3 2.90v 1 2 3 t 50.20% sync sw2 sw1 figure 36 . external synchronization with 120 phase shift 09357-037 ch3 1.00v b w ch2 1.00v b w m2.00ms a ch2 660mv 3 t 43.00% v master v slave figure 37 . c oincident tracking 09357-038 ch1 10.0v ch3 5.00v ch2 10.0v m1.00s a ch3 2.90v 1 2 3 t 50.20% sync sw2 sw1 figure 38 . external synchronization with 90 p hase s hift 09357-039 ch1 10.0v ch3 2.00a ? ch4 2.00a ? ch2 10.0v m1.00s a ch2 5.80v 2 3 1 t 50.00% sw2 i l1 i l2 sw1 figure 39 . dual phase, single output , v out = 3.3 v, i out = 6 a 09357-040 ch3 1.00v b w ch2 1.00v b w m2.00ms a ch2 660mv 3 t 43.00% v master v slave figure 40 . ratiometric tracking
data sheet adp2323 rev. a | page 1 5 of 32 theory of operation the adp2323 is a full featured , dual output , step - down dc - to - dc regulator based on current - mode architecture. it integrates two high - side power mosfet s and two low - side driver s for external mosfet s . the adp2323 targets high performance applications that require high efficiency and design flexibility. the adp2323 can operate with an input voltage from 4.5 v to 20 v, and can regulate the output voltage down to 0. 6 v. addition al features for flexible design include programmable switching frequency, programmable soft start, external compen - sation , independent enable inputs, and power good outputs . control scheme the adp2323 uses a fixed frequency, current - mode pwm control architecture during medium to full loads, but shifts to a power save mo de (pfm) at light loads when the pfm mode is enabled. the po wer save mode reduces switching losses and boosts efficiency under light loads. whe n operating in the fixed frequency pwm mode, the duty cycle of the integrated n - c hannel mosfet (referred to interchangeably as nfet or mosfet) is adjusted , which, in turn, regulates the output voltage. when operating in power save mode, the switching frequ ency is adjusted to regulate the output voltage. pwm mode in pwm mode, the adp2323 operates at a fixed frequency that is set by an external resistor. at the start of each oscillator cycle, the high - side nfet t urns on, placing a positive voltage across the inductor. the inductor current increases until the current sense signal crosses the peak inductor current threshold that turns off the high - side nfet and turns on the low - side nfet (diode). this places a negat ive voltage across the inductor causing the inductor current to reduce. the low - side nfet ( d iode) stays on for the re mainder of the cycle or until the inductor current reaches zero. pfm mode pull the mode pin to ground to enable the pfm mode. when the comp x voltage is below the pfm threshold voltage, the device enters the pfm mode. when the device enters the pfm mode, it monitors the fb x voltage to regulate the output voltage. because the high - side and low - side n fet s are turned off, the output voltage drop s due to the load current discharging the output capacitor. when the fb x voltage drops below 0.605 v, the device starts switching and the output voltage increase s as the output capacitor is charged by the inductor current . when the fb x volta ge exceeds 0.62 v, the device turns off both the high - side a nd low - side n fet s until the fb x voltage drop s to 0.605 v. in the pfm mode , the output voltage ripple is larger than the ripple in the pwm mode. precision enable/shu tdown the adp2323 has two independent enable pin s (en1 and en2) for each channel. the en x pin has an internal pull - down current source (5 a) that provides default turn off when an en x pin is open . when t he voltage on the en 1 or en2 pin exceeds 1.2 v (ty pical ), c hannel 1 or c hannel 2 is enabled and the internal pull - down current source at the en 1 or en2 pin is reduced to 1 a , which allow s the user to program the i nput v oltage undervoltage lockout ( uvlo ) . when the voltage on the en1 or en2 pin drops belo w 1. 1 v (typical) , channel 1 or channel 2 turn s off . when en1 and en2 are both below 1.1 v, all of the internal circuit s turn off and the device enter s the shutdown mode. separate input volta ge s the adp2323 su pport s two separate input voltage s . this means t hat t he pvin1 and pvin2 voltage s can be connected to two different supply voltages. in these types of ap plication s , the pvin1 voltage need s to be above the uvlo voltage before t he pvin2 voltage begins to rise because the pvin1voltage provides the power supply for the internal regulator and control circuitry. this feature makes it possible for a cascading supply operat ion as shown in figure 41, where pvin2 is sourced from the c ha nnel 1 output . in this configuration, the channel 1 outp ut voltage need s to be high enough to maintain c hannel 2 in regulation , and the c hannel 1 output voltage need s to be higher than the input voltage uvlo threshold. sw2 dl2 l2 pvin2 sw1 dl1 pgnd c out1 m 1 l1 pvin1 adp2323 v in v out1 v out2 c out2 m2 09357-043 figure 41 . casc ading supply operation internal regulator ( intvcc) the internal regulator provides a stable voltage supply for the internal control circuits and bias voltage for the low - side gate drive rs. a 1 f ceramic capacitor is recommended to be placed between intvcc and gnd. the internal regulator also includes a current - limit circuit for protection. the in ternal regulator is active when either one of the channel s is enabled. t he pvin1 pin provide s power for the internal regulator that is used by both channels.
adp2323 data sheet rev. a | page 16 of 32 boot strap circuitry the adp2323 integrates the boot regulator s to provide the gate drive voltage for the high - side nfet s. the regulators generate 5 v bootstrap voltage s between the bst x pin and the sw x pin . it is recommended that an x7r or an x5r , 0.1 f ceramic capacitor be placed between the bst x and the sw x pin s. low - side driver the dl x pin provide s the gate drive for the low - side n - channel mosfet . internal circuitry monitors the gate driver signal to ensure br eak - before - make switching to prevent cross conduction. the vdrv pin provides the power supply to the low - side driver s. it is limited to a 5.5 v maximum input , and placing a 1 f ceramic capacitor close to th is pin is recommended. o scillator a resistor fro m rt to gnd program s the switching frequency according to the following equation: f sw [khz] = ] k [ 000 , 60 osc r a 200 k? resistor sets the frequency to 300 k hz , and a 100 k? resistor sets the frequency to 6 00 khz . figure 42 s hows the typical relationship between f sw and r osc . 200 300 400 600 800 500 700 900 1000 1 100 1200 50 90 130 170 210 70 1 10 150 190 230 250 frequenc y (khz) r osc (k?) 09357-044 figure 42 . f sw vs. r osc synchronization t he sync pin can be configured as an input or an output by setting the scfg pin as shown in t able 5 . t able 5 . scfg configuration scfg sync phase shift h igh output 0 gnd input 90 180 k? to gnd input 120 100 k? to gnd input 60 when the sync pin is configured as an output, it generate s a clock with a frequency that is equa l to the internal switching frequency. when the sync pin is configured as an input, the adp2323 synchronize s to the external clock that is applied to the sync pin , and the internal clock must be programmed lower than the external clock. the phase shift can be programmed by the scfg pin . when working in synchronization mode, the adp2323 disable s the pfm mode and works only in the ccm mode. soft start the ssx pin s are used to program the soft start time. place a capacitor between ss x and gnd ; an internal current charge s this capacitor to establish the soft start ramp. the soft start time can be calculated using the following equation: ss ss ss i c v t = 6 . 0 w here: c ss is the soft start capacitance . i ss is the soft start pull - up current (3.5 a) . if the output voltage is prech arged prior to power up , the adp2323 prevents the low - side mosfet from turn ing on until the soft start voltage exceeds the voltage on the fbx pin. during soft start, the adp2323 us es frequency foldback to prevent output current runaway. the switching frequency is reduced according to the voltage present at the fb x pin , which allows more time for the inductor to discharge. the correla tio n between the switching freq uency and the fb x pin voltage is listed in table 6 . table 6 . fbx pin voltage and switching frequency fb x pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v 1/2 f sw v fb < 0.2 v 1/4 f sw peak current - limit and short - circuit p rotection t he adp2323 use s a peak current - limit pr otection circuit to prevent current runaway. place a resis tor between dl x and pgnd to program the current - limit value listed in table 7 . the programmable current - limit threshold feature allows for the use of a small size inductor for low current applications . table 7 . peak current - limit threshold setting r ilim peak current - limit threshold floating 4.8 a 47 k ? 3 a 15 k ? 1.5 a
data sheet adp2323 rev. a | page 17 of 32 t he adp2323 us es hiccup mod e for over current protection. w hen the peak inductor current reaches the current - limit threshold , the high - side mosfet turn s off and the low - side driver turns on until the next cycle while the o ver current counter incr ement s. i f the over current counter reach e s 10, or the fb x pin voltage falls to 0.51 v after the soft start , the device e nter s hiccup mode. during this mode, the high - side mosfet and low - side driver a re both turned off. the device remains in this mode for seven soft start time s and then attempts to restart from soft start . if the current - limit fault is cleared, the device resume s normal oper ation ; o therwise, it reenter s hiccup mode. in some cases, th e input voltage (pvin) ramp rate is too slow or the output cap aci tor is too large to support the setting regu lation voltage during the soft start causing the device to enter the hiccup mode. to avoid such cases, us e a resistor divider at the en x pin to pr ogram the input voltage uvlo or us e a longer soft start time. voltage tracking the adp2323 has a tracking input, trk x , that allows the output voltage to track an external (master) voltage. it allows power sequ encing applicable to fpga s , dsps , and asics , which may require a power sequen ce between the core and the i/o voltage s . the internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the tracking inp ut voltage. the error amplifier regulates the feed back voltage to the lowest of the three voltages. to track a master voltage, tie the trk x pin to a resistor divider from the master voltage as shown in figure 43. fbx trkx swx adp2323 v master r trk_top r trk_bot v slave r top r bot 09357-045 figure 43 . voltage tracking a common application is coincident tracking, which is shown in figure 44 . coincident tracking limits the slave output voltage to be the same as the master voltage until it rea ches regulation. for coincident tracking, set r trk_top = r top and r trk_bot = r bot . time voltage v master v slave 09357-046 figure 44 . coincident tracking ratiometric tracking is shown in figure 45 . the slave output is limited t o a fraction of the master voltage. in this application, the slave and master voltages reach the final value at the same time. time voltage v master v slave 09357-047 figure 45 . ratiometric tracking the ratio of the slave output voltage to the master voltage is a func tion of the two dividers , as follows: bot trk top trk bot top master slave r r r r v v _ _ 1 1 + + = the final trk x pin voltage must be higher than 0.54 v. if the trk function is not used, connect the trk x pin to intvcc. parallel operation adp2323 s upports a two phase parallel operation to provide a single output of 6 a. to configure t he adp2323 as a two phase single output 1. c onnect the fb2 pin to intvcc , thereby disabling the channel 2 error amplifier . 2. con nect comp1 to comp2 and connect en1 to en2. 3. us e ss1 to set the soft start time and keep ss2 open. during parallel operation, the voltages of pvin1 and pvin2 should be the same. power good the power good (pgood x ) pin is an active high, open drain outpu t that indicates if the regulator output voltage is within regulation. high indicates that the voltage at an fb x pin (and , hence, the output voltage) is above 90 % of the reference voltage. low indicates that the voltage at an fb x pin (a nd , hence , the outpu t voltage) is below 85 % of the reference voltage. there is a 16- cycle deglitch time between fb x and pgood x . over v oltage protection the adp2323 provides an overvoltage protection (ovp) featu re to protect the s ystem against the output short ing to a higher voltage supply or when a strong load transient occur s . if the feedback voltage increases to 0.7 v, the internal high - side mosfet and low - side drive r turn off until the voltage at the fb x pin red uces to 0.63 v, at which time the adp2323 resume s normal operation.
adp2323 data sheet rev. a | page 18 of 32 under v oltage lockout the undervoltage lockout ( uvlo ) threshold is 4.2 v with 0.5 v hysteresis to prevent the device from power - on glitches. when the pvin1 or pvin2 voltage rises above 4.2 v , c hannel 1 or channel 2 is enable d and the soft start p eriod initiate s . when either pvin1 or pvin2 drop s below 3.7 v , it turns off c hannel 1 or c hannel 2, respectively . thermal shutdown in the event that the adp2323 junction temperature exceeds 150 c, the thermal shutdown circuit turn s off the regulator . a 1 5 c hysteresis is included so that the adp2323 does not recover from ther mal shutdown until the on - chip tempera ture drops below 1 3 5 c. upon recovery, soft start is initiated prior to normal operation .
data sheet adp2323 rev. a | page 19 of 32 application s information adi sim p ower design tool the adp2323 is supported by the adisimpower design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic and bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count while taking into considera tion the operating conditions and limita tions of the ic and all real external components. for more information about adisimpower design tools, refer to www.analog.com/adisimpower . the tool set is avail able from this website, and users can request an unpopulated board through the tool. input capacitor sele ction the input decoupling capacitor attenuate s high frequency noise on the input and act s as an energy reservoir . this capa citor should be a ceramic capacitor in the range of 10 f to 47 f and must be placed close to the pvin x pin. the loop composed of this input capacitor, high - side n fet , and low - side n fet must be kept as small as possible. the voltage rating of the input capacitor must be greater t han the maximum input voltage. the rms current rating of the input capacitor should be larger than the following equation: ( ) d d i i out rms c in ? = 1 _ output voltage setti ng the output voltage of the adp2323 can be set by an external resistive divider using the following equation: ? ? ? ? ? ? ? ? + = bot top out r r v 1 6 . 0 to limit output voltage accuracy degradation due to fb x pin bias curre nt (0.1 a maximum) to less than 0.5% (maximum) , ensure that r bot is less than 30 k?. table 8 provide s the recommended resist ive divider for various output voltage options. table 8 . resistive divider f or various output voltage s v out (v) r top , 1% ( k?) r bot , 1% ( k?) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 voltage conversion l imitations the minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. the minim um on time of the adp2323 is typically 13 0 n s. the minimum output voltage in ccm mode at a given input voltage and frequency can be calculated by using the following equation: v out_min = v in t min_on f sw ? ( r dson1 ? r dson2 ) i out_min t min_on f sw ? ( r dson2 + r l ) i out_min w here: v out_min is the minimum output voltage . t min_on is th e minimum on time . i out_min is the minimum output current . f s w is the switching frequency . r dson1 is the high - side m osfe t on resistance . r dson2 is the low - side m osfet on resistance . r l is the series resistance of output inductor . the maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. th e minimum off time is typically 150 ns and the maximum duty is typically 90 % in the adp2323 . the maximum output voltage that is limited by the minimum off time at a given input voltage and frequency can be ca lcu lated using the following equation: v out_max = v in (1 C t min_ off f sw ) C ( r dson1 C r dson2 ) i out_max (1 C t min_off f sw ) C ( r dson2 + r l ) i out_max where: v out_max is the maximum output voltage . t min_off is the minimum off time . i out_max is the maximum output current . the maximum output voltage limited by the maximum duty cycle at a given input voltage can be calculated by using the following equation: v out_max = d max v in where d max is the maximum duty . as the previous equa tions show , reduc ing the switching frequency alleviate s the minimum on time and minimum off time limitation. current - limit setting the adp2323 has three selectable current - limit threshold s. make sure that the selected current - limi t value is large r than the peak current of the inductor, i peak .
adp2323 data sheet rev. a | page 20 of 32 inductor selection the inductor value is determined by the operating frequency, input voltage, outp ut voltage, and inductor ripple current . using a small inductor leads to a faster transie nt response but degrade s efficiency d ue to larger inductor ripple current , whereas a large inductor value leads to smaller ripple current and better effi - ciency but results in a slower transient response. thus, there is a tr ade - off between the transient re sponse and efficiency. as a guideline, the inductor ripple current, i l , is typically set to 1/3 of the maximum load current . the inductor value can be calculated using the following equation: ( ) in out l sw vv d l if ? = ? where: v in is the input voltage. v out is the output voltage. i l is the inductor ripple current . f sw is the switching frequency. d is the duty cycle. in out v v d = the adp2323 uses adaptive slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is lar ger than 50%. the internal slope compensation limits the minimum inductor value. for a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: ( ) 1 2 out sw vd f ? the inductor peak current is calculated u sing the following equation: 2 l out peak i i i ? + = the saturation current of the inductor must be larger than the peak inductor current. for the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor s hould be higher than the current - limit threshold of the switch to prevent the inductor from getting into saturation. the rms current of the inductor can be calculated by the following equation: 12 2 2 l out rms i i i ? + = shielded f errite core materials are re commended for low core loss and low emi. table 9 . recommended i nductor s vendor part n o. value [h] i sat [a] i rms [a] dcr [m?] sumida cdrh105rnp - 1r5n 1.5 10.5 8.3 5.8 cdrh105rnp - 2r2n 2.2 9.25 7.5 7.2 cdrh105rnp - 3r3n 3.3 7.8 6 .5 10.4 cdrh105rnp - 4r7n 4.7 6.4 6.1 12.3 cdrh105rnp - 6r8n 6.8 5.4 5.4 18 coilcraft mss1048 - 152nl 1.5 10.5 10.8 5.8 mss1048 - 222nl 2.2 8.4 9.78 7.2 mss1048 - 332nl 3.3 7.38 7.22 10.4 mss1048 - 472nl 4.7 6.46 6.9 12.3 mss1048 - 682nl 6.8 5.94 6.01 18 w urth elektronik 7447797180 1.8 13.3 7.3 16 7447797300 3.0 10.5 7.0 18 7447797470 4.7 8.0 5.8 27 7447797620 6.2 7.5 5.5 30 output capacitor sel ection the output capacitor selection affects both the output voltage ripple and the loop dynamics of the r egulator. for example, d uring load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp up the inductor current, which cause s an und ershoot of the output volta ge. u s e the f ollowing equation to calculate the output capacitance that is required to meet the voltage droop requirement: ( ) uv out out in p ste uv uv out v v v l i k c _ 2 _ 2 ? ? ? = w here: i step is the load step. v out_uv is the allowable undershoot on the output voltage. k uv is a factor, typically setting k uv = 2. another case is when a load is suddenly removed from the output and the energy stored in the inductor rush es into the output ca pacitor, which cause s the output to overshoot. the output capacitance required to meet the overshoot require ment can be calculated using the following equation: 2 _ 22 _ () ov step out ov out out ov out ki l c vv v ? = +? ? w here: v out_ov is the allowable overshoot on the output voltage. k ov is a factor, typically setting k ov = 2. the output ripple is determined by the esr of the output cap acitor and its capacitance value. us e the following equation to select a capacitor that can meet the output ripple requirements : ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _
data sheet adp2323 rev. a | page 21 of 32 w here: v out_r ipple is the allowable output voltage ripple. r esr is the equivalent series resistance of the output capacitor . select the largest output capacitance given by c out_uv , c out_ov , and c out_r ipple to meet both load transient and output ripple performanc e . the selected output capacitor voltage rating must be grea ter than the output voltage. the minimum rms cu rrent rating of the output capacitor is determined by the following equation : 12 _ l rms c i i out ? = low - side power device se lection the adp2323 has integrated low - side m osfet driver s , which can drive the low - side n - c hannel mos fet s (nfet s) . the selection of the low - side n - c hannel mosfet affect s the dc - to - dc regulator performance. the select ed mosfet must meet the following requirement s : ? drain source voltage (v ds ) must be higher than 1.2 v in . ? drain current (i d ) must be great er than the 1.2 i limit _max , where i limit _max is the selected maximum current - limit threshold. the adp2323 low - side gate drive voltage is 5 v. make sure that the selected mosfet can be fully turn ed on at 5 v. total gate charge (qg at 5 v) must be less than 30 nc. lower qg characteristics constitute higher efficiency. w hen the high - side m os fet is turned off , t he l ow - side mos fet carries the inductor current. for low duty cycle application s , the low - side mos fet carries the current for most of the period. to achieve higher efficiency, it is important to select a low on - resistance mos f e t. t he power conduction loss for the low - side mos fet can be calculated using the following equation: p fet_low = i out 2 r dson (1 ? d ) w here r dson is the on resistance of the low - side mos fet . make sure that the mos fet can handle the thermal dissipation due to the power loss. in some cases, efficiency is not critical for the system; therefore, the diode can be selected as the low - side power device. the average current of the diode can be calculated using the following equation: i diode (avg) = (1 ? d ) i out the reverse breakdown voltage rating of the diode must be greater than the input voltage with an app ropriate margin to allow for ring ing , which may be present at the sw x node. a s c hottky diode is recommended because it has low forward voltage drop and fast switching speed . if a diode is used for the low - side device, the adp2323 must ena ble the pfm mode by connecting the mode pin to ground. table 10 . recommended m osfets vendor part no. v ds i d r dson qg fairchild fds8880 30 v 10.7 a 12 m? 12 nc fairchild fdm s 7578 25 v 14 a 8 m? 8 nc fairchild fds6898a 20 v 9.4 a 14 m? 16 nc vishay si4804cdy 30 v 7.9 a 27 m? 7 nc vishay sia430dj 20 v 10.8 a 18.5 m? 5.3 nc aos aon7402 30 v 39 a 15 m? 7.1 nc aos ao4884l 40 v 10 a 16 m? 13.6 nc progr amming uvlo input the p recision enable input can be used to program the uvlo threshold and hysteresis of the input voltage as shown in figure 46. enx 1.2v en cmp 4a 1a pvinx r top_en r bot_en 09357-048 figure 46 . programming uvlo input use th e following equation to calculate r top_en and r bot_en : a 1 v 2 . 1 a 5 v 1 . 1 v 2 . 1 v 1 . 1 _ _ _ ? ? = falling in rising in en top v v r v 2 . 1 5 v 2 . 1 _ _ _ _ ? ? = en top rising in en top en bot r v r r w here : v in_rising is the v in rising threshold . v in_falling is the v in falling threshold. compensation compone nts design for peak current - mode control, the power stage can be simplified as a voltage control led current source supplying current to the output capacitor and load resistor. it is composed of one domain pole and a zero contributed by the output capacitor esr. the control - to - output transfer function is shown in the following equations: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 w here : a vi = 5 a/v r is the load resistance . c out is the output capacitance .
adp2323 data sheet rev. a | page 22 of 32 r esr is the equivalent series resistance of the output capacitor . the adp2323 uses a trans conductance amplifier for the error amplifier to compensate the system. figure 47 show s the simplified peak current - mode control small signal circuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 09357-049 figure 47 . simplified peak current - mode control small signal cir cuit the compensation components , r c and c c , contribute a zero , and the optional c cp and r c contribute an optional pole. the close d - loop transfer equation is as follows : ) ( 1 1 ) ( s g s c c c c r s s c r c c g r r r s t vd cp c cp c c c c cp c m top bot bot v ? ? ? ? ? ? ? ? + + + + ? + = the following design guideline show s how to select the compensation components , r c , c c , and c cp , for ceramic output capacitor application s. 1. determine the cross frequency ( f c ) . generally, the f c is between f s w /12 and f s w /6. 2. r c can be calcula ted using the following equation: vi m c out out c a g f c v r = v 6 . 0 2 3. place the compensation zero at the domain pole ( f p ) . c c can be determined by ( ) c out esr c r c r r c + = 4. c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. c out esr cp r c r c = the adp2323 has a 10 pf capacitor internal ly at the comp x pin ; therefore, if c cp is smaller than 10 p f, n o external capacitor is needed.
data sheet adp2323 rev. a | page 23 of 32 design example this section explains design proced ure and component selection a s shown in figure 50; table 11 provides a list of the required settings . table 11 . dual step - down dc - to - dc regulator requirements parameter specificat ion channel 1 input voltage v in 1 = 12.0 v 10% output voltage v out1 = 1.2 v output current i o ut 1 = 3 a output voltage ripple v out1_ripple = 12 mv load transient 5%, 0.5 a to 3a, 1 a/s channel 2 input voltage v in 2 = 12.0 v 10% output voltag e v out2 = 3.3 v output current i o ut 2 = 3 a output voltage ripple v out 2 _ripple = 33 mv load transient 5%, 0.5 a to 3 a, 1 a/s switching frequency f sw = 5 00 khz output voltage setti ng choose a 10 k ? top feedback resistor (r t op ); calculate the bo ttom feedback resistor by using the following equation: ? ? ? ? ? ? ? ? ? = 6 . 0 6 . 0 out top bot v r r to set the output voltage to 1.2 v, the resistor values are r top1 = 10 k? and r bot1 = 10 k? . to set the output voltage to 3.3 v, t h e resistors values are r top2 = 10 k? and r bot2 = 2. 21 k? . current - limit setting for 3 a output current operation, the typical peak curren t limit is 4.8 a. in this case, no r ilim is required. frequency setting to set the switching frequency to 5 00 khz, use the following equation to calculate the resistor va lue, r osc : ( ) ( ) khz 000 , 60 k sw osc f r = therefore, r osc =100 k?. inductor selection the peak - to - peak inductor ripple current , i l , is set to 30% of the maximum output current. use the f ollowing equation to estimate the value of the inductor : ( ) sw l out in f i d v v l ? ? = for v out1 = 1.2 v, i nductor l1 = 2 .4 h , and f or v out2 = 3.3 v, i nductor l2 = 5.3 h . select the standard inductor value of 2.2 h and 4.7 h for the 1.2 v and 3.3 v rail s. calculate t he peak - to - peak inductor ripple current as follows : ( ) sw out in l f l d v v i ? = ? for v out1 = 1.2 v, i l1 = 0.98 a. for v out2 = 3.3 v, i l2 = 1.02 a . find t he peak inductor current by using the following equation : 2 l out peak i i i ? + = for the 1.2 v rail, t he peak inductor current is 3.49 a , and for the 3.3 v rail, the peak inductor current is 3. 51 a. the rms current through the inductor can be estimated by 12 2 2 l out rms i i i ? + = the rms current of the inductor for both 1.2 v and 3.3 v is approximately 3.01 a. for the 1.2 v rail, select an inductor with a minimum rms current rating of 3.01 a and a min imum s aturation current rating of 3.49 a. for the 3.3 v rail, select an inductor with a minimum rms current rating of 3.01 a and a minimum s aturation current rating of 3.51 a. based on these requirements, for the 1.2 v rail , select a 2.2 h inductor , such as the sumida cdrh105rnp - 2r2n , with a dcr = 7.2 m? ; for the 3.3 v rail, select a 4.7 h inductor , such as the sumida cdrh105rnp - 4r7n , with a dcr = 12.3 m? . output capacitor sel ection the output capacitor is required to meet the output voltage ripple and l oad transient requirement. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capacitance: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r _ ? = f or v out1 = 1.2 v, c out_r ipple 1 = 20 f and r esr1 = 12 m? . for v out2 = 3.3 v, c out_r ipple 2 = 7.7 f and r esr2 = 3 2 m?. to meet the 5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: ( ) 2 2 _ 2 _ out ov out out step ov ov out v v v l i k c ? ? + ? = ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = for estimation purpose s , use k ov = k uv = 2. for v ou t1 = 1.2 v, use c out_ov1 = 191 f and c o ut_uv1 = 21 f. for v out2 = 3.3 v, use c out_ov2 = 54 f and c out_uv2 = 20 f.
adp2323 data sheet rev. a | page 24 of 32 fo r the 1.2 v rail, the output capacitor esr need s to be smaller than 12 m? , and the output capacitance need s to be larger than 191 f. it is r ecommend that three pieces of 100 f/x5r/6.3 v ceramic capacitor be used, such as the grm32er60j107me20 f rom murata , with an esr = 2 m? . for the 3.3 v rail, the esr of the output capacitor must be smaller than 32 m? and the output capacitance must be larger than 54 f. it is r ecommend ed that two pieces of 47 f/x5r/6.3 v ceramic capacitor be used , such as the murata grm32er60j476me20, with an esr = 2 m? . low - s ide mos fet selection a l ow r dson n - c hannel mos fet is selected for high effi ciency solutions. t he mos fet break down voltage need s to be great er than 1.2 v v in , and the d rain current need s to be greater than 1.2 v i l imit . it is r ecommend ed that a 30 v , n - c hannel mos fet be used , such as the fds8880 from fairchild. the r dson of the fds8880 at a 4.5 v driver voltage is 12 m? , and the total gate charge is 12 nc. compensation compone nts for better load transient and stability performance, set the cross frequency, f c , to f s w /10. in this case, f sw is running at 5 00 khz ; therefore, the f c is set to 5 0 khz. for the 1.2 v rail , t he 100 f ceramic output capacitor has a derated value of 64 f . k 4 . 80 a/v 5 s 300 v 6 . 0 khz 50 f 64 3 v 2 . 1 2 = = c1 r ( ) pf 957 k 4 . 80 f 64 3 001 . 0 4 . 0 = + = 1 c c pf 4 . 2 k 4 . 80 f 64 3 001 . 0 = = cp1 c c hoose standard components , r c1 = 82 k? and c c1 = 100 0 pf . n o c cp1 is needed. figure 48 shows th e 1.2 v rail bode plot at 3 a. the cross frequency is 49 khz and the phase margin is 59 . ?60 ?48 ?36 ?24 ?12 0 12 24 36 48 60 magnitude (db) ?180 ?144 ?108 ?72 ?36 0 36 72 108 144 180 phase (degrees) 09357-148 1k 10k 100k 1m frequenc y (hz) figure 48 . bode plot for 1.2 v r ail for the 3.3 v rail , the 47f ceramic output capacitor has a derated value of 32 f . k 7 . 73 a/v 5 s 300 v 6 . 0 khz 50 f 32 2 v 3 . 3 2 = = c2 r ( ) pf 956 k 7 . 73 f 32 2 001 . 0 1 . 1 = + = 2 c c pf 1 k 7 . 73 f 32 2 001 . 0 = = cp2 c choose standard component values of r c2 = 75 k? and c c2 = 1000 p f. n o c cp2 is needed . figure 49 shows the 3.3 v rail bode plot at 3 a. the cross frequency is 59 khz and phase margin is 61 . ?60 ?48 ?36 ?24 ?12 0 12 24 36 48 60 magnitude (db) ?180 ?144 ?108 ?72 ?36 0 36 72 108 144 180 phase (degrees) 09357-149 1k 10k 100k 1m frequenc y (hz) figure 49 . bode plot for 3.3 v r ail soft start time prog r am ming the soft start feature allows the output voltage to ramp up in a con trolled manner, eliminating output voltage o vershoot during soft start and limiting inrush current. the soft start time is set to 3 ms. nf 5 . 17 v 6 . 0 ms 3 a 5 . 3 v 6 . 0 = = = ss ss ss t i c choose a standard comp onent value of c ss1 = c ss2 = 22 n f. input capacitor sele ction a minimum 10 f ceramic capacitor i s required, place d near the pvin x pin. in this application, one piece of 10 f, x5r, 25 v ceramic capacitor is recommended.
data sheet adp2323 rev. a | page 25 of 32 external components recommendatio n table 12. recommended external components for typical a pplication s with 3 a output current f s w (khz) v in (v) v out ( v ) l ( h ) c out ( f ) 1 r top ( k? ) r bot ( k? ) r c ( k? ) c c ( pf ) c cp (pf) 300 12 1 3.3 330 10 15 62 1500 33 12 1.2 4.7 3 30 10 10 82 1500 22 12 1.5 4.7 330 15 10 100 1500 22 12 1.8 4.7 2 100 20 10 47 1500 4.7 12 2.5 6.8 100 + 47 47.5 15 47 1500 4.7 12 3.3 10 100 + 47 10 2.21 62 1500 3.3 12 5 10 100 22 3 62 1500 2.2 5 1 3.3 330 10 15 6 2 1500 33 5 1.2 3.3 330 1 0 10 82 1500 22 5 1.5 3.3 330 15 10 100 1500 22 5 1.8 4.7 2 100 20 10 47 1500 4.7 5 2.5 4.7 100 + 47 47.5 15 47 1500 4.7 5 3.3 4.7 100 10 2.21 47 1500 3.3 600 12 1.5 2.2 2 100 15 10 82 820 2.2 12 1.8 3.3 100 + 47 20 10 75 820 3.3 12 2.5 3. 3 2 47 47.5 15 62 820 2.2 12 3.3 4.7 2 47 10 2.21 82 820 2.2 12 5 4.7 47 22 3 62 820 2.2 5 1 1.5 2 100 10 15 56 820 2.2 5 1.2 1.5 2 100 10 10 62 820 2.2 5 1.5 2.2 100 + 47 15 10 62 820 2.2 5 1.8 2.2 2 47 20 10 47 820 2.2 5 2.5 2.2 2 47 47.5 15 62 820 2.2 5 3.3 2.2 2 47 10 2.21 82 820 2.2 1000 12 1.8 1.5 100 20 10 82 470 2.2 12 2.5 2.2 47 47.5 15 56 470 2.2 12 3.3 2.2 47 10 2.21 68 470 2.2 12 5 3.3 47 22 3 100 470 2.2 5 1 1 2 100 10 15 82 470 2.2 5 1.2 1 100 + 47 10 10 82 470 2.2 5 1.5 1 2 47 15 10 68 470 2.2 5 1.8 1 2 47 20 10 82 470 2.2 5 2.5 1 47 47.5 15 56 470 2.2 5 3.3 1 47 10 2.21 62 470 2.2 1 330 f: 6.3 v, sanyo 6tpd330m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20.
adp2323 data sheet rev. a | page 26 of 32 typical application circuit s intvcc r t op1 10k? c c1 1000pf r c1 82k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 2.2h m1 fds8880 m2 fds8880 l2 4.7h v in 12v v in 12v v out1 1.2 v , 3 a c out1 100f c out4 47f v out2 3.3 v , 3 a r bot1 10k? r t op2 10k? r c2 75k? c c2 1000pf c ss2 22nf c in2 10 f , 25v r bot2 2.21k? r osc 120k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 c out2 100f c out5 47f c out3 100f 09357-050 figure 50 . using external m osfet application , v in1 = v in2 = 12 v, v out1 = 1.2 v, i out1 = 3 a , v out 2 = 3.3 v, i out 2 = 3 a, f sw = 500 khz intvcc r t op1 22k? c c1 1.2nf r c1 75k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 8.2h d1 b220 a d2 b220 a l2 8.2h v in 12v v in 12v v out1 5v , 2 a c out1 22f c out3 22f v out2 3.3 v , 1.5 a r bot1 3k? r t op2 10k? r c2 47k? c c2 1.5nf c ss2 22nf c in2 10 f , 25v r bot2 2.21k? r osc 100k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 mode c out2 22f r ilim2 47k? c out4 22f 09357-051 figure 51 . using external diode application , v in1 = v in2 = 12 v, v out1 = 5 v, i out1 = 2 a , v out 2 = 3.3 v, i out 2 = 1.5 a , f sw = 600 kh z
data sheet adp2323 rev. a | page 27 of 32 trk1 r top1 20k ? c c1 470pf r c1 150k ? r ok1 100k ? r osc 100k ? c ss1 22nf c int 1f c in1 10f, 25v c bst1 0.1f c bst2 0.1f l1 1h m1 fds8880 m2 fds8880 l2 1h v in 12v v in 12v v out1 1.8v, 6a c out1 100f r bot1 10k ? c in2 10f, 25v fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 pvin2 bst2 pgood1 scfg sync intvcc adp2323 rt mode pgood2 trk2 gnd sw1 sw1 sw2 dl1 pgnd dl2 sw2 vdrv pvin1 c out2 100f c out3 100f r ok2 100k ? c drv 1f 09357-052 figure 52. parallel single output application, v in = 12 v, v out = 1.8 v, i out = 6 a, f sw = 600 khz m1 intvcc r top1 22k ? c c1 390pf r c1 62k? c ss1 22nf c int 1f c drv 1f c in1 10f, 25v c bst1 0.1f c bst2 0.1f l1 3.3h l2 1h v in 12v v out1 5v, 2a c out2 100f v out2 1.0v, 3a r bot1 3k? r top2 10k? r c2 82k? c c2 390pf c ss2 22nf c in2 10f, 25v r bot2 15k? r osc 50k ? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdrv adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 c out1 22f c out3 100f m1 fds6898a 09357-053 figure 53. cascading supply application, v in1 = 12 v, v out1 = 5 v, i out1 = 2 a, v out2 = 1 v, i out2 = 3 a, f sw = 1.2 mhz
adp2323 data sheet rev. a | page 28 of 32 intvcc r t op1 20k? c c1 820pf r c1 75k? c ss1 22nf c int1 1f c dr v1 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 3.3h m1 fds8880 m2 fds8880 l2 4.7h v in 12v v in 12v v out1 1.8 v , 3 a c out1 100f c out3 47f v out2 3.3 v , 3 a r bot1 10k? r t op2 10k? r c2 82k? c c2 820pf c ss2 22nf c in2 10 f , 25v r bot2 2.21k? r osc1 100k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 rt sw1 dl1 pgnd dl2 sw2 c out2 47f c out4 47f intvcc sync sync r t op3 20k? c c3 820pf r c3 75k? c ss3 22nf c int2 1f c dr v2 1f c in1 10 f , 25v c bst3 0.1f c bst4 0.1f l3 3.3h m3 fds8880 m4 fds8880 l4 4.7h v in 12v v in 12v v out3 1.8 v , 3 a c out5 100f c out7 47f v out4 3.3 v , 3 a r bot3 10k? r t op4 10k? r c4 82k? c c4 820pf c ss4 22nf c in4 10 f , 25v r bot4 2.21k? r osc2 120k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 c out6 47f c out8 47f 09357-054 figure 54 . synchronization with 90 phase s hi f t b etween each channel
data sheet adp2323 rev. a | page 29 of 32 intvcc r t op1 15k? c c1 820pf r c1 68k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 2.2h m1 fds8880 m2 fds8880 l2 3.3h v in 9v v in 9v v out1 1.5 v , 3 a c out1 47f c out4 47f v out2 2.5 v , 3 a r bot1 10k? r t op2 47.5k? r c2 75k? c c2 820pf c ss2 22nf c in2 10 f , 25v r bot2 15k? r osc 100k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 mode c out2 47f c out5 47f c out3 47f 09357-055 figure 55 . enable pfm mode with mode pin pull ed to gnd , v in1 = v in2 = 9 v, v out1 = 1.5 v, i out1 = 3 a , v out 2 = 2.5 v, i out 2 = 3 a , f sw = 600 khz intvcc r t op1 10k? c c1 1500pf r c1 100k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 8.2h m1 fds8880 m2 fds8880 l2 5.6h v in 12v v in 12v v out1 3.3 v , 3 a c out1 100f c out3 100f v out2 1.8 v , 3 a r bot1 2.21k? r en_bot 68k? r en_ t op 330k? r t op2 20k? r c2 51k? c c2 1500pf c ss2 22nf c in2 10 f , 25v r bot2 10k? r osc 200k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 mode scfg trk2 trk1 vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 r pgood1 100k? c out2 100f c out4 100f 09357-056 figure 56 . p rogrammable v in_rising = 8.7 v, v in_fall ing = 6.7 v, 3.3 v start up before 1.8 v , v in1 = v in2 = 12 v, v out1 = 3.3 v, i out1 = 3 a , v out 2 = 1.8 v, i out 2 = 3 a , f sw = 300 khz
adp2323 data sheet rev. a | page 30 of 32 intvcc r t op1 47.5k? c c1 1000pf r c1 68k? c ss1 22nf c int 1f c dr v 1f c in1 10 f , 25v c bst1 0.1f c bst2 0.1f l1 4.7h m1 fds8880 m2 fds8880 l2 2.2h v in 12v v in 12v v out1 2.5 v , 3 a c out1 47f c out3 100f v out2 1.25 v , 3 a r bot1 15k? r trk_ t op 47.5k? r trk_bot 15k? r t op2 13k? r c2 58k? c c2 1000pf c ss2 10nf c in2 10 f , 25v r bot2 12k? r osc 120k? fb1 comp1 ss1 en1 pvin1 bst1 fb2 comp2 ss2 en2 pvin2 bst2 trk2 mode scfg vdr v adp2323 gnd pgood2 pgood1 sync rt sw1 dl1 pgnd dl2 sw2 trk2 c out2 47f c out4 100f 09357-057 figure 57 . channel 2 tracking with c hannel 1 v in1 = v in2 = 12 v, v out1 = 2.5 v, i out1 = 3 a , v out 2 = 1.25 v, i out 2 = 3 a, f sw = 500 khz
data sheet adp2323 rev. a | page 31 of 32 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 58 . 32 - lead lead frame chip scale package [ lfcsp _ wq ] 5 mm 5 mm body, very very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guid e model 1 temperature range output voltage package description package option adp2323acpz -r7 ? 40 c to +125 c a djustable 32- lead lfcsp_ w q cp -32-7 adp2323 -ev a l z evaluation board 1 z = rohs compliant part.
adp2323 data sheet rev. a | page 32 of 32 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09357 - 0- 6/12(a)

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